* ARM architected timer

ARM Cortex-A7 and Cortex-A15 have a per-core architected timer, which
provides a per-cpu local timer.

The timer is attached to a GIC to deliver its two per-processor
interrupts (one for the secure mode, one for the non-secure mode).

** Timer node properties:

- compatible : Should be "arm,armv7-timer"

- interrupts : One or two interrupts for secure and non-secure mode

- clock-frequency : The frequency of the main counter, in Hz. Optional.

Example:

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 13 0xf08 1 14 0xf08>;
		clock-frequency = <100000000>;
	};
