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tmdlHdmiTx_Types.h

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00001  /**
00002  * Copyright (C) 2007 NXP N.V., All Rights Reserved.
00003  * This source code and any compilation or derivative thereof is the proprietary
00004  * information of NXP N.V. and is confidential in nature. Under no circumstances
00005  * is this software to be  exposed to or placed under an Open Source License of
00006  * any type without the expressed written permission of NXP N.V.
00007  *
00008  * \file          tmdlHdmiTx_Types.h
00009  *
00010  * \version       $Revision: 1 $
00011  *
00012  * \date          $Date: 02/08/07 08:32 $
00013  *
00014  * \brief         devlib driver component API for the TDA998x HDMI Transmitters
00015  *
00016  * \section refs  Reference Documents
00017  * HDMI Tx Driver - FRS.doc,
00018  * HDMI Tx Driver - tmdlHdmiTx - SCS.doc
00019  *
00020  * \section info  Change Information
00021  *
00022  * \verbatim
00023 
00024    $History: tmdlHdmiTx_Types.h $
00025  *
00026  * *****************  Version 1  *****************
00027  * User: Demoment     Date: 02/08/07   Time: 08:32
00028  * Updated in $/Source/tmdlHdmiTx/inc
00029  * initial version
00030 
00031    \endverbatim
00032  *
00033 */
00034 
00035 #ifndef TMDLHDMITX_TYPES_H
00036 #define TMDLHDMITX_TYPES_H
00037 
00038 /*============================================================================*/
00039 /*                       INCLUDE FILES                                        */
00040 /*============================================================================*/
00041 
00042 #include "tmNxTypes.h"
00043 
00044 #ifdef __cplusplus
00045 extern "C" {
00046 #endif
00047 
00048 /*============================================================================*/
00049 /*                       MACRO DEFINITIONS                                    */
00050 /*============================================================================*/
00051 
00052 /*============================================================================*/
00053 /*                                DEFINES                                     */
00054 /*============================================================================*/
00055 
00056 /**< Error Codes */
00057 #define TMDL_ERR_DLHDMITX_BASE                      CID_DL_HDMITX
00058 #define TMDL_ERR_DLHDMITX_COMP                      (TMDL_ERR_DLHDMITX_BASE | TM_ERR_COMP_UNIQUE_START)
00059 
00060 #define TMDL_ERR_DLHDMITX_COMPATIBILITY             (TMDL_ERR_DLHDMITX_BASE + TM_ERR_COMPATIBILITY)             /**< SW Interface compatibility   */
00061 #define TMDL_ERR_DLHDMITX_MAJOR_VERSION             (TMDL_ERR_DLHDMITX_BASE + TM_ERR_MAJOR_VERSION)             /**< SW Major Version error       */
00062 #define TMDL_ERR_DLHDMITX_COMP_VERSION              (TMDL_ERR_DLHDMITX_BASE + TM_ERR_COMP_VERSION)              /**< SW component version error   */
00063 #define TMDL_ERR_DLHDMITX_BAD_UNIT_NUMBER           (TMDL_ERR_DLHDMITX_BASE + TM_ERR_BAD_UNIT_NUMBER)           /**< Invalid device unit number   */
00064 #define TMDL_ERR_DLHDMITX_BAD_INSTANCE              (TMDL_ERR_DLHDMITX_BASE + TM_ERR_BAD_INSTANCE)              /**< Bad input instance value     */
00065 #define TMDL_ERR_DLHDMITX_BAD_HANDLE                (TMDL_ERR_DLHDMITX_BASE + TM_ERR_BAD_HANDLE)                /**< Bad input handle             */
00066 #define TMDL_ERR_DLHDMITX_BAD_PARAMETER             (TMDL_ERR_DLHDMITX_BASE + TM_ERR_BAD_PARAMETER)             /**< Invalid input parameter      */
00067 #define TMDL_ERR_DLHDMITX_NO_RESOURCES              (TMDL_ERR_DLHDMITX_BASE + TM_ERR_NO_RESOURCES)              /**< Resource is not available    */
00068 #define TMDL_ERR_DLHDMITX_RESOURCE_OWNED            (TMDL_ERR_DLHDMITX_BASE + TM_ERR_RESOURCE_OWNED)            /**< Resource is already in use   */
00069 #define TMDL_ERR_DLHDMITX_RESOURCE_NOT_OWNED        (TMDL_ERR_DLHDMITX_BASE + TM_ERR_RESOURCE_NOT_OWNED)        /**< Caller does not own resource */
00070 #define TMDL_ERR_DLHDMITX_INCONSISTENT_PARAMS       (TMDL_ERR_DLHDMITX_BASE + TM_ERR_INCONSISTENT_PARAMS)       /**< Inconsistent input params    */
00071 #define TMDL_ERR_DLHDMITX_NOT_INITIALIZED           (TMDL_ERR_DLHDMITX_BASE + TM_ERR_NOT_INITIALIZED)           /**< Component is not initialized */
00072 #define TMDL_ERR_DLHDMITX_NOT_SUPPORTED             (TMDL_ERR_DLHDMITX_BASE + TM_ERR_NOT_SUPPORTED)             /**< Function is not supported    */
00073 #define TMDL_ERR_DLHDMITX_INIT_FAILED               (TMDL_ERR_DLHDMITX_BASE + TM_ERR_INIT_FAILED)               /**< Initialization failed        */
00074 #define TMDL_ERR_DLHDMITX_BUSY                      (TMDL_ERR_DLHDMITX_BASE + TM_ERR_BUSY)                      /**< Component is busy            */
00075 #define TMDL_ERR_DLHDMITX_I2C_READ                  (TMDL_ERR_DLHDMITX_BASE + TM_ERR_READ)                      /**< Read error                   */
00076 #define TMDL_ERR_DLHDMITX_I2C_WRITE                 (TMDL_ERR_DLHDMITX_BASE + TM_ERR_WRITE)                     /**< Write error                  */
00077 #define TMDL_ERR_DLHDMITX_FULL                      (TMDL_ERR_DLHDMITX_BASE + TM_ERR_FULL)                      /**< Queue is full                */
00078 #define TMDL_ERR_DLHDMITX_NOT_STARTED               (TMDL_ERR_DLHDMITX_BASE + TM_ERR_NOT_STARTED)               /**< Function is not started      */
00079 #define TMDL_ERR_DLHDMITX_ALREADY_STARTED           (TMDL_ERR_DLHDMITX_BASE + TM_ERR_ALREADY_STARTED)           /**< Function is already started  */
00080 #define TMDL_ERR_DLHDMITX_ASSERTION                 (TMDL_ERR_DLHDMITX_BASE + TM_ERR_ASSERTION)                 /**< Assertion failure            */
00081 #define TMDL_ERR_DLHDMITX_INVALID_STATE             (TMDL_ERR_DLHDMITX_BASE + TM_ERR_INVALID_STATE)             /**< Invalid state for function   */
00082 #define TMDL_ERR_DLHDMITX_OPERATION_NOT_PERMITTED   (TMDL_ERR_DLHDMITX_BASE + TM_ERR_OPERATION_NOT_PERMITTED)   /**< Corresponds to posix EPERM   */
00083 #define TMDL_ERR_DLHDMITX_RESOLUTION_UNKNOWN        (TMDL_ERR_DLHDMITX_BASE + TM_ERR_BAD_FORMAT)                /**< Bad format                   */
00084 
00085 #define TMDL_DLHDMITX_HDCP_SECURE               (TMDL_ERR_DLHDMITX_COMP + 0x0001) /**< Revocation list is secure */
00086 #define TMDL_DLHDMITX_HDCP_NOT_SECURE           (TMDL_ERR_DLHDMITX_COMP + 0x0002) /**< Revocation list is NOT secure */
00087 
00088 
00089 /*============================================================================*/
00090 /*                       ENUM OR TYPE DEFINITIONS                             */
00091 /*============================================================================*/
00092 
00093 /**
00094  * \brief Enum listing all events that can be signalled to application
00095  */
00096 typedef enum
00097 {
00098     TMDL_HDMITX_HDCP_ACTIVE         = 0,    /**< HDCP encryption status switched to active */
00099     TMDL_HDMITX_HDCP_INACTIVE       = 1,    /**< HDCP encryption status switched to inactive */
00100     TMDL_HDMITX_HPD_ACTIVE          = 2,    /**< Hotplug status switched to active */
00101     TMDL_HDMITX_HPD_INACTIVE        = 3,    /**< Hotplug status switched to inactive */
00102     TMDL_HDMITX_RX_KEYS_RECEIVED    = 4,    /**< Receiver(s) key(s) received */
00103     TMDL_HDMITX_RX_DEVICE_ACTIVE    = 5,    /**< Rx device is connected and active */
00104     TMDL_HDMITX_RX_DEVICE_INACTIVE  = 6,    /**< Rx device is connected but inactive (standby) */
00105     TMDL_HDMITX_EDID_RECEIVED       = 7,    /**< EDID has been received */
00106     TMDL_HDMITX_VS_RPT_RECEIVED     = 8,    /**< VS interrupt has been received */              
00107 #ifdef HDMI_TX_REPEATER_ISR_MODE
00108     TMDL_HDMITX_B_STATUS            = 9,    /**< TX received BStatus */
00109 #endif /* HDMI_TX_REPEATER_ISR_MODE */
00110     TMDL_HDMITX_DEBUG_EVENT_1       = 10     /**< This is a debug event */
00111 } tmdlHdmiTxEvent_t;
00112 
00113 /**
00114  * \brief Enum listing all available event status
00115  */
00116 typedef enum
00117 {
00118     TMDL_HDMITX_EVENT_ENABLED,  /**< Event is enabled */
00119     TMDL_HDMITX_EVENT_DISABLED  /**< Event is disabled */
00120 } tmdlHdmiTxEventStatus_t;
00121 
00122 /**
00123  * \brief Callback function pointer type, used to allow driver to callback
00124           application when activity status is changing at input.
00125  * \param Event Identifier of the source event.
00126  */
00127 typedef void (*ptmdlHdmiTxCallback_t) (tmdlHdmiTxEvent_t event);
00128 
00129 /**
00130  * \brief Enum listing all supported device versions
00131  */
00132  typedef enum
00133  {
00134      TMDL_HDMITX_DEVICE_UNKNOWN,   /**< HW device is unknown */
00135      TMDL_HDMITX_DEVICE_TDA9984,   /**< HW device is IC TDA9984 */
00136      TMDL_HDMITX_DEVICE_TDA9989,   /**< HW device is IC TDA9989 */
00137      TMDL_HDMITX_DEVICE_TDA9981,   /**< HW device is IC TDA9981 */
00138      TMDL_HDMITX_DEVICE_TDA9983,   /**< HW device is IC TDA9983 */
00139      TMDL_HDMITX_DEVICE_TDA19989   /**< HW device is IC TDA19989 */
00140 
00141  } tmdlHdmiTxDeviceVersion_t;
00142 
00143 /**
00144  * \brief Enum defining the supported HDMI standard version
00145  */
00146 typedef enum
00147 {
00148    TMDL_HDMITX_HDMI_VERSION_UNKNOWN, /**< Unknown   */
00149    TMDL_HDMITX_HDMI_VERSION_1_1,     /**< HDMI 1.1  */
00150    TMDL_HDMITX_HDMI_VERSION_1_2a,    /**< HDMI 1.2a */
00151    TMDL_HDMITX_HDMI_VERSION_1_3a     /**< HDMI 1.3  */
00152 } tmdlHdmiTxHdmiVersion_t;
00153 
00154 /**
00155  * \brief Enum listing all color depth (8 bits/color, 10 bits/color, etc.)
00156  */
00157 typedef enum
00158 {
00159     TMDL_HDMITX_COLORDEPTH_24   = 0,    /**< 8 bits per color */
00160     TMDL_HDMITX_COLORDEPTH_30   = 1,    /**< 10 bits per color */
00161     TMDL_HDMITX_COLORDEPTH_36   = 2,    /**< 12 bits per color */
00162     TMDL_HDMITX_COLORDEPTH_48   = 3     /**< 16 bits per color */
00163 } tmdlHdmiTxColorDepth_t;
00164 
00165 /**
00166  * \brief Enum defining the EDID Status
00167  */
00168 typedef enum
00169 {
00170     TMDL_HDMITX_EDID_READ                = 0,   /**< All blocks read OK */
00171     TMDL_HDMITX_EDID_READ_INCOMPLETE     = 1,   /**< All blocks read OK but buffer too small to return all of them */
00172     TMDL_HDMITX_EDID_ERROR_CHK_BLOCK_0   = 2,   /**< Block 0 checksum error */
00173     TMDL_HDMITX_EDID_ERROR_CHK           = 3,   /**< Block 0 OK, checksum error in one or more other blocks */
00174     TMDL_HDMITX_EDID_NOT_READ            = 4,   /**< EDID not read */
00175     TMDL_HDMITX_EDID_STATUS_INVALID      = 5    /**< Invalid   */
00176 } tmdlHdmiTxEdidStatus_t;
00177 
00178 /**
00179  * \brief Structure defining the supported audio packets
00180  */
00181 typedef struct
00182 {
00183    Bool HBR;              /**< High Bitrate Audio packet */
00184    Bool DST;              /**< Direct Stream Transport audio packet */
00185    Bool oneBitAudio;      /**< One Bit Audio sample packet */
00186 } tmdlHdmiTxAudioPacket_t;
00187 
00188 /**
00189  * \brief Enum listing all possible audio input formats
00190  */
00191 typedef enum
00192 {
00193     TMDL_HDMITX_AFMT_SPDIF      = 0, /**< SPDIF */
00194     TMDL_HDMITX_AFMT_I2S        = 1, /**< I2S */
00195     TMDL_HDMITX_AFMT_OBA        = 2, /**< One bit audio / DSD */
00196     TMDL_HDMITX_AFMT_DST        = 3, /**< DST */
00197     TMDL_HDMITX_AFMT_HBR        = 4  /**< HBR */
00198 } tmdlHdmiTxAudioFormat_t;
00199 
00200 /**
00201  * \brief Enum listing all possible audio input sample rates
00202  */
00203 typedef enum
00204 {
00205     TMDL_HDMITX_AFS_32K           = 0, /**< 32kHz    */
00206     TMDL_HDMITX_AFS_44K           = 1, /**< 44.1kHz  */
00207     TMDL_HDMITX_AFS_48K           = 2, /**< 48kHz    */
00208     TMDL_HDMITX_AFS_88K           = 3, /**< 88.2kHz  */
00209     TMDL_HDMITX_AFS_96K           = 4, /**< 96kHz    */
00210     TMDL_HDMITX_AFS_176K          = 5, /**< 176.4kHz */
00211     TMDL_HDMITX_AFS_192K          = 6  /**< 192kHz   */
00212 } tmdlHdmiTxAudioRate_t;
00213 
00214 /**
00215  * \brief Enum listing all possible audio input sample rates
00216  */
00217 typedef enum
00218 {
00219     TMDL_HDMITX_I2SQ_16BITS       = 16, /**< 16 bits */
00220     TMDL_HDMITX_I2SQ_32BITS       = 32, /**< 32 bits */
00221     TMDL_HDMITX_I2SQ_OTHERS       = 0   /**< for SPDIF and DSD */
00222 } tmdlHdmiTxAudioI2SQualifier_t;
00223 
00224 /**
00225  * \brief Enum listing all possible audio I2S formats
00226  */
00227 typedef enum
00228 {
00229     TMDL_HDMITX_I2SFOR_PHILIPS_L   = 0, /**< Philips like format */
00230     TMDL_HDMITX_I2SFOR_OTH_L       = 2, /**< Other non Philips left justified */
00231     TMDL_HDMITX_I2SFOR_OTH_R       = 3, /**< Other non Philips right justified */
00232     TMDL_HDMITX_I2SFOR_INVALID     = 4  /**< Invalid format */
00233 } tmdlHdmiTxAudioI2SFormat_t;
00234 
00235 /**
00236  * \brief Enum listing all possible DST data transfer rates 
00237  */
00238 typedef enum
00239 {
00240     TMDL_HDMITX_DSTRATE_SINGLE  = 0,    /**< Single transfer rate */
00241     TMDL_HDMITX_DSTRATE_DOUBLE  = 1     /**< Double data rate */
00242 } tmdlHdmiTxDstRate_t;
00243 
00244 /**
00245  * \brief Structure describing unit capabilities
00246  */
00247 typedef struct
00248 {
00249     tmdlHdmiTxDeviceVersion_t   deviceVersion;  /**< HW device version */
00250     tmdlHdmiTxHdmiVersion_t     hdmiVersion;    /**< Supported HDMI standard version  */
00251     tmdlHdmiTxAudioPacket_t     audioPacket;    /**< Supported audio packets */
00252     tmdlHdmiTxColorDepth_t      colorDepth;     /**< Supported color depth */
00253     Bool                        hdcp;           /**< Supported Hdcp encryption (True/False) */
00254     Bool                        scaler;         /**< Supported scaler (True/False) */
00255 } tmdlHdmiTxCapabilities_t;
00256 
00257 /**
00258  * \brief Structure gathering all instance setup parameters
00259  */
00260 typedef struct
00261 {
00262     Bool    simplayHd;          /**< Enable simplayHD support */
00263     Bool    repeaterEnable;     /**< Enable repeater mode */
00264     UInt8   *pEdidBuffer;       /**< Pointer to raw EDID data */
00265     UInt32  edidBufferSize;     /**< Size of buffer for raw EDID data */
00266 } tmdlHdmiTxInstanceSetupInfo_t;
00267 
00268 /**
00269  * \brief Enum listing all IA/CEA 861-D video formats
00270  */
00271 typedef enum
00272 {
00273     TMDL_HDMITX_VFMT_NULL               = 0,    /**< Not a valid format...        */
00274     TMDL_HDMITX_VFMT_NO_CHANGE          = 0,    /**< ...or no change required     */
00275     TMDL_HDMITX_VFMT_MIN                = 1,    /**< Lowest valid format          */
00276     TMDL_HDMITX_VFMT_TV_MIN             = 1,    /**< Lowest valid TV format       */
00277     TMDL_HDMITX_VFMT_01_640x480p_60Hz   = 1,    /**< Format 01 640  x 480p  60Hz  */
00278     TMDL_HDMITX_VFMT_02_720x480p_60Hz   = 2,    /**< Format 02 720  x 480p  60Hz  */
00279     TMDL_HDMITX_VFMT_03_720x480p_60Hz   = 3,    /**< Format 03 720  x 480p  60Hz  */
00280     TMDL_HDMITX_VFMT_04_1280x720p_60Hz  = 4,    /**< Format 04 1280 x 720p  60Hz  */
00281     TMDL_HDMITX_VFMT_05_1920x1080i_60Hz = 5,    /**< Format 05 1920 x 1080i 60Hz  */
00282     TMDL_HDMITX_VFMT_06_720x480i_60Hz   = 6,    /**< Format 06 720  x 480i  60Hz  */
00283     TMDL_HDMITX_VFMT_07_720x480i_60Hz   = 7,    /**< Format 07 720  x 480i  60Hz  */
00284     TMDL_HDMITX_VFMT_08_720x240p_60Hz   = 8,    /**< Format 08 720  x 240p  60Hz  */
00285     TMDL_HDMITX_VFMT_09_720x240p_60Hz   = 9,    /**< Format 09 720  x 240p  60Hz  */
00286     TMDL_HDMITX_VFMT_10_720x480i_60Hz   = 10,   /**< Format 10 720  x 480i  60Hz  */
00287     TMDL_HDMITX_VFMT_11_720x480i_60Hz   = 11,   /**< Format 11 720  x 480i  60Hz  */
00288     TMDL_HDMITX_VFMT_12_720x240p_60Hz   = 12,   /**< Format 12 720  x 240p  60Hz  */
00289     TMDL_HDMITX_VFMT_13_720x240p_60Hz   = 13,   /**< Format 13 720  x 240p  60Hz  */
00290     TMDL_HDMITX_VFMT_14_1440x480p_60Hz  = 14,   /**< Format 14 1440 x 480p  60Hz  */
00291     TMDL_HDMITX_VFMT_15_1440x480p_60Hz  = 15,   /**< Format 15 1440 x 480p  60Hz  */
00292     TMDL_HDMITX_VFMT_16_1920x1080p_60Hz = 16,   /**< Format 16 1920 x 1080p 60Hz  */
00293     TMDL_HDMITX_VFMT_17_720x576p_50Hz   = 17,   /**< Format 17 720  x 576p  50Hz  */
00294     TMDL_HDMITX_VFMT_18_720x576p_50Hz   = 18,   /**< Format 18 720  x 576p  50Hz  */
00295     TMDL_HDMITX_VFMT_19_1280x720p_50Hz  = 19,   /**< Format 19 1280 x 720p  50Hz  */
00296     TMDL_HDMITX_VFMT_20_1920x1080i_50Hz = 20,   /**< Format 20 1920 x 1080i 50Hz  */
00297     TMDL_HDMITX_VFMT_21_720x576i_50Hz   = 21,   /**< Format 21 720  x 576i  50Hz  */
00298     TMDL_HDMITX_VFMT_22_720x576i_50Hz   = 22,   /**< Format 22 720  x 576i  50Hz  */
00299     TMDL_HDMITX_VFMT_23_720x288p_50Hz   = 23,   /**< Format 23 720  x 288p  50Hz  */
00300     TMDL_HDMITX_VFMT_24_720x288p_50Hz   = 24,   /**< Format 24 720  x 288p  50Hz  */
00301     TMDL_HDMITX_VFMT_25_720x576i_50Hz   = 25,   /**< Format 25 720  x 576i  50Hz  */
00302     TMDL_HDMITX_VFMT_26_720x576i_50Hz   = 26,   /**< Format 26 720  x 576i  50Hz  */
00303     TMDL_HDMITX_VFMT_27_720x288p_50Hz   = 27,   /**< Format 27 720  x 288p  50Hz  */
00304     TMDL_HDMITX_VFMT_28_720x288p_50Hz   = 28,   /**< Format 28 720  x 288p  50Hz  */
00305     TMDL_HDMITX_VFMT_29_1440x576p_50Hz  = 29,   /**< Format 29 1440 x 576p  50Hz  */
00306     TMDL_HDMITX_VFMT_30_1440x576p_50Hz  = 30,   /**< Format 30 1440 x 576p  50Hz  */
00307     TMDL_HDMITX_VFMT_31_1920x1080p_50Hz = 31,   /**< Format 31 1920 x 1080p 50Hz  */
00308     TMDL_HDMITX_VFMT_32_1920x1080p_24Hz = 32,   /**< Format 32 1920 x 1080p 24Hz  */
00309     TMDL_HDMITX_VFMT_33_1920x1080p_25Hz = 33,   /**< Format 33 1920 x 1080p 25Hz  */
00310     TMDL_HDMITX_VFMT_34_1920x1080p_30Hz = 34,   /**< Format 34 1920 x 1080p 30Hz  */
00311     TMDL_HDMITX_VFMT_35_2880x480p_60Hz  = 35,   /**< Format 35 2880 x 480p  60Hz 4:3  */
00312     TMDL_HDMITX_VFMT_36_2880x480p_60Hz  = 36,   /**< Format 36 2880 x 480p  60Hz 16:9 */
00313     TMDL_HDMITX_VFMT_37_2880x576p_50Hz  = 37,   /**< Format 37 2880 x 576p  50Hz 4:3  */
00314     TMDL_HDMITX_VFMT_38_2880x576p_50Hz  = 38,   /**< Format 38 2880 x 576p  50Hz 16:9 */
00315 
00316     TMDL_HDMITX_VFMT_TV_MAX             = 38,   /**< Highest valid TV format      */
00317     TMDL_HDMITX_VFMT_TV_NO_REG_MIN      = 32,   /**< Lowest TV format without prefetched table */
00318     TMDL_HDMITX_VFMT_TV_NUM             = 39,   /**< Number of TV formats & null  */
00319 
00320     TMDL_HDMITX_VFMT_PC_MIN             = 128,  /**< Lowest valid PC format       */
00321     TMDL_HDMITX_VFMT_PC_640x480p_60Hz   = 128,  /**< PC format 128                */
00322     TMDL_HDMITX_VFMT_PC_800x600p_60Hz   = 129,  /**< PC format 129                */
00323     TMDL_HDMITX_VFMT_PC_1152x960p_60Hz  = 130,  /**< PC format 130                */
00324     TMDL_HDMITX_VFMT_PC_1024x768p_60Hz  = 131,  /**< PC format 131                */
00325     TMDL_HDMITX_VFMT_PC_1280x768p_60Hz  = 132,  /**< PC format 132                */
00326     TMDL_HDMITX_VFMT_PC_1280x1024p_60Hz = 133,  /**< PC format 133                */
00327     TMDL_HDMITX_VFMT_PC_1360x768p_60Hz  = 134,  /**< PC format 134                */
00328     TMDL_HDMITX_VFMT_PC_1400x1050p_60Hz = 135,  /**< PC format 135                */
00329     TMDL_HDMITX_VFMT_PC_1600x1200p_60Hz = 136,  /**< PC format 136                */
00330     TMDL_HDMITX_VFMT_PC_1024x768p_70Hz  = 137,  /**< PC format 137                */
00331     TMDL_HDMITX_VFMT_PC_640x480p_72Hz   = 138,  /**< PC format 138                */
00332     TMDL_HDMITX_VFMT_PC_800x600p_72Hz   = 139,  /**< PC format 139                */
00333     TMDL_HDMITX_VFMT_PC_640x480p_75Hz   = 140,  /**< PC format 140                */
00334     TMDL_HDMITX_VFMT_PC_1024x768p_75Hz  = 141,  /**< PC format 141                */
00335     TMDL_HDMITX_VFMT_PC_800x600p_75Hz   = 142,  /**< PC format 142                */
00336     TMDL_HDMITX_VFMT_PC_1024x864p_75Hz  = 143,  /**< PC format 143                */
00337     TMDL_HDMITX_VFMT_PC_1280x1024p_75Hz = 144,  /**< PC format 144                */
00338     TMDL_HDMITX_VFMT_PC_640x350p_85Hz   = 145,  /**< PC format 145                */
00339     TMDL_HDMITX_VFMT_PC_640x400p_85Hz   = 146,  /**< PC format 146                */
00340     TMDL_HDMITX_VFMT_PC_720x400p_85Hz   = 147,  /**< PC format 147                */
00341     TMDL_HDMITX_VFMT_PC_640x480p_85Hz   = 148,  /**< PC format 148                */
00342     TMDL_HDMITX_VFMT_PC_800x600p_85Hz   = 149,  /**< PC format 149                */
00343     TMDL_HDMITX_VFMT_PC_1024x768p_85Hz  = 150,  /**< PC format 150                */
00344     TMDL_HDMITX_VFMT_PC_1152x864p_85Hz  = 151,  /**< PC format 151                */
00345     TMDL_HDMITX_VFMT_PC_1280x960p_85Hz  = 152,  /**< PC format 152                */
00346     TMDL_HDMITX_VFMT_PC_1280x1024p_85Hz = 153,  /**< PC format 153                */
00347     TMDL_HDMITX_VFMT_PC_1024x768i_87Hz  = 154,  /**< PC format 154                */
00348     TMDL_HDMITX_VFMT_PC_MAX             = 154,  /**< Highest valid PC format      */
00349     TMDL_HDMITX_VFMT_PC_NUM             = (1+154-128)   /**< Number of PC formats         */
00350 } tmdlHdmiTxVidFmt_t;
00351 
00352 /**
00353  * \brief Structure defining the EDID short video descriptor
00354  */
00355 typedef struct
00356 {
00357     tmdlHdmiTxVidFmt_t  videoFormat;            /**< Video format as defined by EIA/CEA 861-D */
00358     Bool                nativeVideoFormat;   /**< True if format is the preferred video format */
00359 } tmdlHdmiTxShortVidDesc_t;
00360 
00361 /**
00362  * \brief Enum listing all picture aspect ratio (H:V) (4:3, 16:9)
00363  */
00364 typedef enum
00365 {
00366     TMDL_HDMITX_P_ASPECT_RATIO_UNDEFINED    = 0,    /**< Undefined picture aspect ratio */
00367     TMDL_HDMITX_P_ASPECT_RATIO_6_5          = 1,    /**< 6:5 picture aspect ratio (PAR) */
00368     TMDL_HDMITX_P_ASPECT_RATIO_5_4          = 2,    /**< 5:4 PAR */
00369     TMDL_HDMITX_P_ASPECT_RATIO_4_3          = 3,    /**< 4:3 PAR */
00370     TMDL_HDMITX_P_ASPECT_RATIO_16_10        = 4,    /**< 16:10 PAR */
00371     TMDL_HDMITX_P_ASPECT_RATIO_5_3          = 5,    /**< 5:3 PAR */
00372     TMDL_HDMITX_P_ASPECT_RATIO_16_9         = 6,    /**< 16:9 PAR */
00373     TMDL_HDMITX_P_ASPECT_RATIO_9_5          = 7     /**< 9:5 PAR */
00374 } tmdlHdmiTxPictAspectRatio_t;
00375 
00376 /**
00377  * \brief Enum listing all vertical frequency
00378  */
00379 typedef enum
00380 {
00381     TMDL_HDMITX_VFREQ_24Hz      = 0,    /**< 24Hz          */
00382     TMDL_HDMITX_VFREQ_25Hz      = 1,    /**< 25Hz          */
00383     TMDL_HDMITX_VFREQ_30Hz      = 2,    /**< 30Hz          */
00384     TMDL_HDMITX_VFREQ_50Hz      = 3,    /**< 50Hz          */
00385     TMDL_HDMITX_VFREQ_59Hz      = 4,    /**< 59.94Hz       */
00386     TMDL_HDMITX_VFREQ_60Hz      = 5,    /**< 60Hz          */
00387 #ifndef FORMAT_PC
00388     TMDL_HDMITX_VFREQ_INVALID   = 6,    /**< Invalid       */
00389     TMDL_HDMITX_VFREQ_NUM       = 6     /**< No. of values */
00390 #else /* FORMAT_PC */
00391     TMDL_HDMITX_VFREQ_70Hz      = 6,    /**< 70Hz          */
00392     TMDL_HDMITX_VFREQ_72Hz      = 7,    /**< 72Hz          */
00393     TMDL_HDMITX_VFREQ_75Hz      = 8,    /**< 75Hz          */
00394     TMDL_HDMITX_VFREQ_85Hz      = 9,    /**< 85Hz          */
00395     TMDL_HDMITX_VFREQ_87Hz      = 10,   /**< 87Hz          */
00396     TMDL_HDMITX_VFREQ_INVALID   = 11,   /**< Invalid       */
00397     TMDL_HDMITX_VFREQ_NUM       = 11    /**< No. of values */
00398 #endif /* FORMAT_PC */
00399 } tmdlHdmiTxVfreq_t;
00400 
00401 /**
00402  * \brief Structure storing specifications of a video resolution
00403  */
00404 typedef struct
00405 {
00406     UInt16                      width;         /**< Width of the frame in pixels */
00407     UInt16                      height;        /**< Height of the frame in pixels */
00408     Bool                        interlaced;    /**< Interlaced mode (True/False) */
00409     tmdlHdmiTxVfreq_t           vfrequency;    /**< Vertical frequency in Hz */
00410     tmdlHdmiTxPictAspectRatio_t aspectRatio;   /**< Picture aspect ratio (H:V) */
00411 } tmdlHdmiTxVidFmtSpecs_t;
00412 
00413 /**
00414  * \brief Enum listing all video input modes (CCIR, RGB, etc.)
00415  */
00416 typedef enum
00417 {
00418     TMDL_HDMITX_VINMODE_CCIR656     = 0,    /**< CCIR656 */
00419     TMDL_HDMITX_VINMODE_RGB444      = 1,    /**< RGB444  */
00420     TMDL_HDMITX_VINMODE_YUV444      = 2,    /**< YUV444  */
00421     TMDL_HDMITX_VINMODE_YUV422      = 3,    /**< YUV422  */
00422     TMDL_HDMITX_VINMODE_NO_CHANGE   = 4,    /**< No change */
00423     TMDL_HDMITX_VINMODE_INVALID     = 5     /**< Invalid */
00424 } tmdlHdmiTxVinMode_t;
00425 
00426 /**
00427  * \brief Enum listing all possible sync sources
00428  */
00429 typedef enum
00430 {
00431     TMDL_HDMITX_SYNCSRC_EMBEDDED = 0, /**< Embedded sync */
00432     TMDL_HDMITX_SYNCSRC_EXT_VREF = 1, /**< External sync Vref, Href, Fref */
00433     TMDL_HDMITX_SYNCSRC_EXT_VS   = 2  /**< External sync Vs, Hs */
00434 } tmdlHdmiTxSyncSource_t;
00435 
00436 /**
00437  * \brief Enum listing all output pixel rate (Single, Double, etc.)
00438  */
00439 typedef enum
00440 {
00441     TMDL_HDMITX_PIXRATE_DOUBLE          = 0,        /**< Double pixel rate */
00442     TMDL_HDMITX_PIXRATE_SINGLE          = 1,        /**< Single pixel rate */
00443     TMDL_HDMITX_PIXRATE_SINGLE_REPEATED = 2         /**< Single pixel repeated */
00444 } tmdlHdmiTxPixRate_t;
00445 
00446 /**
00447  * \brief Structure defining the video input configuration
00448  */
00449 typedef struct
00450 {
00451    tmdlHdmiTxVidFmt_t       format;     /**< Video format as defined by EIA/CEA 861-D */
00452    tmdlHdmiTxVinMode_t      mode;       /**< Video mode (CCIR, RGB, YUV, etc.) */
00453    tmdlHdmiTxSyncSource_t   syncSource; /**< Sync source type */
00454    tmdlHdmiTxPixRate_t      pixelRate;  /**< Pixel rate */
00455 } tmdlHdmiTxVideoInConfig_t;
00456 
00457 /**
00458  * \brief Enum listing all video output modes (YUV, RGB, etc.)
00459  */
00460 typedef enum
00461 {
00462     TMDL_HDMITX_VOUTMODE_RGB444     = 0,    /**< RGB444    */
00463     TMDL_HDMITX_VOUTMODE_YUV422     = 1,    /**< YUV422    */
00464     TMDL_HDMITX_VOUTMODE_YUV444     = 2     /**< YUV444    */
00465 } tmdlHdmiTxVoutMode_t;
00466 
00467 /**
00468  * \brief Enum defining possible quantization range
00469  */
00470 typedef enum
00471 {
00472     TMDL_HDMITX_VQR_DEFAULT = 0, /* Follow HDMI spec. */
00473     TMDL_HDMITX_RGB_FULL    = 1, /* Force RGB FULL , DVI only */
00474     TMDL_HDMITX_RGB_LIMITED = 2  /* Force RGB LIMITED , DVI only */
00475 } tmdlHdmiTxVQR_t;
00476 
00477 
00478 /**
00479  * \brief Structure defining the video output configuration
00480  */
00481 typedef struct
00482 {
00483    tmdlHdmiTxVidFmt_t       format;     /**< Video format as defined by EIA/CEA 861-D */
00484    tmdlHdmiTxVoutMode_t     mode;       /**< Video mode (CCIR, RGB, YUV, etc.) */
00485    tmdlHdmiTxColorDepth_t   colorDepth; /**< Color depth */
00486    tmdlHdmiTxVQR_t          dviVqr;     /**< VQR applied in DVI mode */ 
00487 } tmdlHdmiTxVideoOutConfig_t;
00488 
00489 /**
00490  * \brief Structure defining the audio input configuration
00491  */
00492 typedef struct
00493 {
00494    tmdlHdmiTxAudioFormat_t          format;             /**< Audio format (I2S, SPDIF, etc.) */
00495    tmdlHdmiTxAudioRate_t            rate;               /**< Audio sampling rate */
00496    tmdlHdmiTxAudioI2SFormat_t       i2sFormat;          /**< I2S format of the audio input */
00497    tmdlHdmiTxAudioI2SQualifier_t    i2sQualifier;       /**< I2S qualifier of the audio input (8,16,32 bits) */
00498    tmdlHdmiTxDstRate_t              dstRate;            /**< DST data transfer rate */
00499    UInt8                            channelAllocation;  /**< Ref to CEA-861D p85 */
00500 } tmdlHdmiTxAudioInConfig_t;
00501 
00502 /**
00503  * \brief Enum listing all the type of sunk
00504  */
00505 typedef enum
00506 {
00507     TMDL_HDMITX_SINK_DVI  = 0, /**< DVI  */
00508     TMDL_HDMITX_SINK_HDMI = 1, /**< HDMI */
00509     TMDL_HDMITX_SINK_EDID = 2  /**< As currently defined in EDID */
00510 } tmdlHdmiTxSinkType_t;
00511 
00512 /**
00513  * \brief Structure defining the content of a gamut packet
00514  */
00515 typedef struct
00516 {
00517     Bool   nextField;           /**< Gamut relevant for field following packet insertion */
00518     UInt8  GBD_Profile;         /**< Profile of the gamut packet : 0 = P0, 1 = P1 */
00519     UInt8  affectedGamutSeqNum; /**< Gamut sequence number of the field that have to be affected by this gamut packet */
00520     Bool   noCurrentGBD;        /**< Current field not using specific gamut */
00521     UInt8  currentGamutSeqNum;  /**< Gamut sequence number of the current field */
00522     UInt8  packetSequence;      /**< Sequence of the packet inside a multiple packet gamut */
00523     UInt8  payload[28];         /**< Payload of the gamut packet */
00524 } tmdlHdmiTxGamutData_t;
00525 
00526 /**
00527  * \brief Type defining the content of a generic packet
00528  */
00529 typedef UInt8 tmdlHdmiTxGenericPacket[28];
00530 
00531 /**
00532  * \brief Structure defining the content of an ACP packet
00533  */
00534 typedef struct
00535 {
00536     UInt8 acpType;
00537     UInt8 acpData[28];
00538 } tmdlHdmiTxAcpPktData_t;
00539 
00540 /**
00541  * \brief Structure defining the content of an AVI infoframe
00542  */
00543 typedef struct
00544 {
00545     UInt8  colorIndicator;                /**< RGB or YCbCr indicator. See CEA-861-B table 8 for details */
00546     UInt8  activeInfoPresent;             /**< Active information present. Indicates if activeFormatAspectRatio field is valid */
00547     UInt8  barInformationDataValid;       /**< Bar information data valid */
00548     UInt8  scanInformation;               /**< Scan information. See CEA-861-B table 8 for details */
00549     UInt8  colorimetry;                   /**< Colorimetry. See CEA-861-B table 9 for details */
00550     UInt8  pictureAspectRatio;            /**< Picture aspect ratio. See CEA-861-B table 9 for details */
00551     UInt8  activeFormatAspectRatio;       /**< Active Format aspect ratio. See CEA-861-B table 10 and Annex H for details */
00552     UInt8  nonUniformPictureScaling;      /**< Non-uniform picture scaling. See CEA-861-B table 11 for details */
00553     UInt8  videoFormatIdentificationCode; /**< Video format indentification code. See CEA-861-B section 6.3 for details */
00554     UInt8  pixelRepetitionFactor;         /**< Pixel repetition factor. See CEA-861-B table 11 for details */
00555     UInt16 lineNumberEndTopBar;
00556     UInt16 lineNumberStartBottomBar;
00557     UInt16 lineNumberEndLeftBar;
00558     UInt16 lineNumberStartRightBar;
00559 } tmdlHdmiTxAviIfData_t;
00560 
00561 /**
00562  * \brief Structure defining the content of an ACP packet
00563  */
00564 typedef struct
00565 {
00566     Bool avMute;
00567 } tmdlHdmiTxGcpPktData_t;
00568 
00569 /**
00570  * \brief Structure defining the content of an AUD infoframe
00571  */
00572 typedef struct
00573 {
00574     UInt8 codingType;        /**< Coding type (always set to zero) */
00575     UInt8 channelCount;      /**< Channel count. See CEA-861-B table 17 for details */
00576     UInt8 samplefrequency;   /**< Sample frequency. See CEA-861-B table 18 for details */
00577     UInt8 sampleSize;        /**< Sample frequency. See CEA-861-B table 18 for details */
00578     UInt8 channelAllocation; /**< Channel allocation. See CEA-861-B section 6.3.2 for details */
00579     Bool  downmixInhibit;    /**< Downmix inhibit. See CEA-861-B section 6.3.2 for details */
00580     UInt8 levelShiftValue;   /**< level shift value for downmixing. See CEA-861-B section 6.3.2 and table 23 for details */
00581 } tmdlHdmiTxAudIfData_t;
00582 
00583 /**
00584  * \brief Structure defining the content of an ISRC1 packet
00585  */
00586 typedef struct
00587 {
00588     Bool  isrcCont;         /**< ISRC packet continued in next packet */
00589     Bool  isrcValid;        /**< Set to one when ISRCStatus and UPC_EAN_ISRC_xx are valid */
00590     UInt8 isrcStatus;       /**< ISRC status */
00591     UInt8 UPC_EAN_ISRC[16]; /**< ISRC packet data */
00592 } tmdlHdmiTxIsrc1PktData_t;
00593 
00594 /**
00595  * \brief Structure defining the content of an ISRC2 packet
00596  */
00597 typedef struct
00598 {
00599     UInt8 UPC_EAN_ISRC[16];  /**< ISRC packet data */
00600 } tmdlHdmiTxIsrc2PktData_t;
00601 
00602 /**
00603  * \brief Structure defining the content of an MPS infoframe
00604  */
00605 typedef struct
00606 {
00607     UInt32 bitRate;         /**< MPEG bit rate in Hz */
00608     UInt32 frameType;       /**< MPEG frame type */
00609     Bool   fieldRepeat;     /**< 0: new field, 1:repeated field */
00610 } tmdlHdmiTxMpsIfData_t;
00611 
00612 /**
00613  * \brief Structure defining the content of an SPD infoframe
00614  */
00615 typedef struct
00616 {
00617     UInt8   vendorName[8];   /**< Vendor name */
00618     UInt8   productDesc[16]; /**< Product Description */
00619     UInt32  sourceDevInfo;   /**< Source Device Info */
00620 } tmdlHdmiTxSpdIfData_t;
00621 
00622 /**
00623  * \brief Structure defining the content of a VS packet
00624  */
00625 typedef struct
00626 {
00627     UInt8 version;
00628     UInt8 vsData[27];
00629 } tmdlHdmiTxVsPktData_t;
00630 
00631 /**
00632  * \brief Structure defining the Edid audio descriptor
00633  */
00634 typedef struct
00635 {
00636     UInt8 format;         /* EIA/CEA861 mode */
00637     UInt8 channels;       /* number of channels */
00638     UInt8 supportedFreqs; /* bitmask of supported frequencies */
00639     UInt8 supportedRes;   /* bitmask of supported resolutions (LPCM only) */
00640     UInt8 maxBitrate;     /* Maximum bitrate divided by 8KHz (compressed formats only) */
00641 } tmdlHdmiTxEdidAudioDesc_t;
00642 
00643 /**
00644  * \brief Structure defining detailed timings of a video format
00645  */
00646 typedef struct
00647 {
00648     UInt16  pixelClock;        /**< Pixel Clock/10 000         */
00649     UInt16  hActivePixels;     /**< Horizontal Active Pixels   */
00650     UInt16  hBlankPixels;      /**< Horizontal Blanking Pixels */
00651     UInt16  vActiveLines;      /**< Vertical Active Lines      */
00652     UInt16  vBlankLines;       /**< Vertical Blanking Lines    */
00653     UInt16  hSyncOffset;       /**< Horizontal Sync Offset     */
00654     UInt16  hSyncWidth;        /**< Horiz. Sync Pulse Width    */
00655     UInt16  vSyncOffset;       /**< Vertical Sync Offset       */
00656     UInt16  vSyncWidth;        /**< Vertical Sync Pulse Width  */
00657     UInt16  hImageSize;        /**< Horizontal Image Size      */
00658     UInt16  vImageSize;        /**< Vertical Image Size        */
00659     UInt16  hBorderPixels;     /**< Horizontal Border          */
00660     UInt16  vBorderPixels;     /**< Vertical Border            */
00661     UInt8   flags;             /**< Interlace/sync info        */
00662 } tmdlHdmiTxEdidVideoTimings_t;
00663 
00664 /** size descriptor block of monitor descriptor */
00665 #define EDID_MONITOR_DESCRIPTOR_SIZE   13
00666 
00667 /**
00668  * \brief Structure defining the first monitor descriptor
00669  */
00670 typedef struct
00671 {   
00672     Bool    descRecord;                                 /**< True when parameters of struct are available   */
00673     UInt8   monitorName[EDID_MONITOR_DESCRIPTOR_SIZE];  /**< Monitor Name                                   */
00674 } tmdlHdmiTxEdidFirstMD_t;
00675 
00676 /**
00677  * \brief Structure defining the second monitor descriptor
00678  */
00679 typedef struct
00680 {
00681     Bool    descRecord;             /**< True when parameters of struct are available   */
00682     UInt8   minVerticalRate;        /**< Min vertical rate in Hz                        */
00683     UInt8   maxVerticalRate;        /**< Max vertical rate in Hz                        */
00684     UInt8   minHorizontalRate;      /**< Min horizontal rate in Hz                      */
00685     UInt8   maxHorizontalRate;      /**< Max horizontal rate in Hz                      */
00686     UInt8   maxSupportedPixelClk;   /**< Max suuported pixel clock rate in MHz          */
00687 } tmdlHdmiTxEdidSecondMD_t;
00688 
00689 /**
00690  * \brief Structure defining the other monitor descriptor
00691  */
00692 typedef struct
00693 {
00694     Bool    descRecord;                                     /**< True when parameters of struct are available   */
00695     UInt8   otherDescriptor[EDID_MONITOR_DESCRIPTOR_SIZE];  /**< Other monitor Descriptor                       */
00696 } tmdlHdmiTxEdidOtherMD_t;
00697 
00698 /**
00699  * \brief Test pattern types
00700  */
00701 typedef enum
00702 {
00703     TMDL_HDMITX_PATTERN_OFF     = 0, /**< Insert test pattern       */
00704     TMDL_HDMITX_PATTERN_CBAR4   = 1, /**< Insert 4-bar colour bar   */
00705     TMDL_HDMITX_PATTERN_CBAR8   = 2, /**< Insert 8-bar colour bar   */
00706     TMDL_HDMITX_PATTERN_BLUE    = 3, /**< Insert Blue screen        */
00707     TMDL_HDMITX_PATTERN_BLACK   = 4, /**< Insert Black screen       */
00708     TMDL_HDMITX_PATTERN_INVALID = 5  /**< Invalid pattern           */
00709 } tmdlHdmiTxTestPattern_t;
00710 
00711 /**
00712  * \brief Enum listing all hdcp state
00713  */
00714 typedef enum
00715 {
00716     TMDL_HDMITX_HDCP_CHECK_NOT_STARTED       = 0,    /**< Check not started */
00717     TMDL_HDMITX_HDCP_CHECK_IN_PROGRESS       = 1,    /**< No failures, more to do */
00718     TMDL_HDMITX_HDCP_CHECK_PASS              = 2,    /**< Final check has passed */
00719     TMDL_HDMITX_HDCP_CHECK_FAIL_FIRST        = 3,    /**< First check failure code */
00720     TMDL_HDMITX_HDCP_CHECK_FAIL_DRIVER_STATE = 3,    /**< Driver not AUTHENTICATED */
00721     TMDL_HDMITX_HDCP_CHECK_FAIL_DEVICE_T0    = 4,    /**< A T0 interrupt occurred */
00722     TMDL_HDMITX_HDCP_CHECK_FAIL_DEVICE_RI    = 5,    /**< Device RI changed */
00723     TMDL_HDMITX_HDCP_CHECK_FAIL_DEVICE_FSM   = 6,    /**< Device FSM not 10h */
00724     TMDL_HDMITX_HDCP_CHECK_NUM               = 7     /**< Number of check results */
00725 }tmdlHdmiTxHdcpCheck_t;
00726 
00727 /**
00728  * \brief Enum listing all hdcp option flags
00729  */
00730 typedef enum
00731 {
00732     TMDL_HDMITX_HDCP_OPTION_FORCE_PJ_IGNORED    = 0x01, /* Not set: obey PJ result     */
00733     TMDL_HDMITX_HDCP_OPTION_FORCE_SLOW_DDC      = 0x02, /* Not set: obey BCAPS setting */
00734     TMDL_HDMITX_HDCP_OPTION_FORCE_NO_1_1        = 0x04, /* Not set: obey BCAPS setting */
00735     TMDL_HDMITX_HDCP_OPTION_FORCE_REPEATER      = 0x08, /* Not set: obey BCAPS setting */
00736     TMDL_HDMITX_HDCP_OPTION_FORCE_NO_REPEATER   = 0x10, /* Not set: obey BCAPS setting */
00737     TMDL_HDMITX_HDCP_OPTION_FORCE_V_EQU_VBAR    = 0x20, /* Not set: obey V=V' result   */
00738     TMDL_HDMITX_HDCP_OPTION_FORCE_VSLOW_DDC     = 0x40, /* Set: 50kHz DDC */
00739     TMDL_HDMITX_HDCP_OPTION_DEFAULT             = 0x00, /* All the above Not Set vals */
00740     TMDL_HDMITX_HDCP_OPTION_MASK                = 0x7F, /* Only these bits are allowed */
00741     TMDL_HDMITX_HDCP_OPTION_MASK_BAD            = 0x80  /* These bits are not allowed  */
00742 }tmdlHdmiTxHdcpOptions_t;
00743 
00744 #ifndef NO_HDCP
00745 /** KSV list sizes */
00746 typedef enum
00747 {
00748     TMDL_HDMITX_KSV_LIST_MAX_DEVICES = 128,
00749     TMDL_HDMITX_KSV_BYTES_PER_DEVICE = 5
00750 } tmdlHdmiTxHdcpHandleSHA_1;
00751 
00752 /**
00753  * \brief Structure defining information about hdcp
00754  */
00755 typedef struct
00756 {
00757     tmdlHdmiTxHdcpCheck_t   hdcpCheckState;                                 /* Hdcp check state */
00758     UInt8                   hdcpErrorState;                                 /* Error State when T0 occured */
00759     Bool                    bKsvSecure;                                     /* BKSV is secured */
00760     UInt8                   hdcpBksv[TMDL_HDMITX_KSV_BYTES_PER_DEVICE];     /* BKSV read from B sink */
00761     UInt8                   hdcpKsvList[TMDL_HDMITX_KSV_BYTES_PER_DEVICE *
00762                                         TMDL_HDMITX_KSV_LIST_MAX_DEVICES];  /* KSV list read from B sink during
00763                                                                             SHA-1 interrupt */
00764     UInt8                   hdcpKsvDevices;                                 /* Number of devices read from
00765                                                                             B sink during SHA-1 interrupt */
00766     UInt8                   hdcpDeviceDepth;                               /* Connection tree depth */
00767     Bool                    hdcpMaxCascExceeded;
00768     Bool                    hdcpMaxDevsExceeded;
00769 } tmdlHdmiTxHdcpInfo_t;
00770 #endif /* NO_HDCP */
00771 
00772 /**
00773  * \brief Enum defining possible HDCP
00774  */
00775 typedef enum
00776 {
00777     TMDL_HDMITX_HDCP_OK = 0,
00778     TMDL_HDMITX_HDCP_BKSV_RCV_FAIL,                   /* Source does not receive Sink BKsv  */
00779     TMDL_HDMITX_HDCP_BKSV_CHECK_FAIL,                 /* BKsv does not contain 20 zeros and 20 ones */
00780     TMDL_HDMITX_HDCP_BCAPS_RCV_FAIL,                  /* Source does not receive Sink Bcaps */
00781     TMDL_HDMITX_HDCP_AKSV_SEND_FAIL,                  /* Source does not send AKsv */
00782     TMDL_HDMITX_HDCP_R0_RCV_FAIL,                     /* Source does not receive R'0 */
00783     TMDL_HDMITX_HDCP_R0_CHECK_FAIL,                   /* R0 = R'0 check fail */
00784     TMDL_HDMITX_HDCP_BKSV_NOT_SECURE,
00785     TMDL_HDMITX_HDCP_RI_RCV_FAIL,                     /* Source does not receive R'i */
00786     TMDL_HDMITX_HDCP_RPT_RI_RCV_FAIL,                 /* Source does not receive R'i repeater mode */
00787     TMDL_HDMITX_HDCP_RI_CHECK_FAIL,                   /* RI = R'I check fail */
00788     TMDL_HDMITX_HDCP_RPT_RI_CHECK_FAIL,               /* RI = R'I check fail repeater mode */
00789     TMDL_HDMITX_HDCP_RPT_BCAPS_RCV_FAIL,              /* Source does not receive Sink Bcaps repeater mode */
00790     TMDL_HDMITX_HDCP_RPT_BCAPS_READY_TIMEOUT,
00791     TMDL_HDMITX_HDCP_RPT_V_RCV_FAIL,                  /* Source does not receive V'*/
00792     TMDL_HDMITX_HDCP_RPT_BSTATUS_RCV_FAIL,            /* Source does not receive BSTATUS repeater mode */
00793     TMDL_HDMITX_HDCP_RPT_KSVLIST_RCV_FAIL,            /* Source does not receive Ksv list in repeater mode */
00794     TMDL_HDMITX_HDCP_RPT_KSVLIST_NOT_SECURE,
00795     TMDL_HDMITX_HDCP_UNKNOWN_STATUS
00796 
00797 }tmdlHdmiTxHdcpStatus_t;
00798 
00799 
00800 /**
00801  * \brief EDID information about sink latency
00802  */
00803 typedef struct
00804 {
00805     Bool   latency_available;
00806     Bool   Ilatency_available;
00807     UInt8  Edidvideo_latency;
00808     UInt8  Edidaudio_latency;
00809     UInt8  EdidIvideo_latency;
00810     UInt8  EdidIaudio_latency;
00811 
00812 } tmdlHdmiTxEdidLatency_t;
00813 
00814 
00815 /**
00816  * \brief Enum defining possible HotPlug status
00817  */
00818 typedef enum
00819 {
00820     TMDL_HDMITX_HOTPLUG_INACTIVE    = 0,    /**< Hotplug inactive */
00821     TMDL_HDMITX_HOTPLUG_ACTIVE      = 1,    /**< Hotplug active   */
00822     TMDL_HDMITX_HOTPLUG_INVALID     = 2     /**< Invalid Hotplug  */
00823 } tmdlHdmiTxHotPlug_t;
00824 
00825 
00826 /**
00827  * \brief Enum defining possible RxSense status
00828  */
00829 typedef enum
00830 {
00831     TMDL_HDMITX_RX_SENSE_INACTIVE    = 0,    /**< RxSense inactive */
00832     TMDL_HDMITX_RX_SENSE_ACTIVE      = 1,    /**< RxSense active   */
00833     TMDL_HDMITX_RX_SENSE_INVALID     = 2     /**< Invalid RxSense  */
00834 } tmdlHdmiTxRxSense_t;
00835 
00836 
00837 #ifdef __cplusplus
00838 }
00839 #endif
00840 
00841 #endif /* TMDLHDMITX_TYPES_H */
00842 
00843 /*============================================================================*/
00844 /*                            END OF FILE                                     */
00845 /*============================================================================*/
00846 

Hdmi version Tx_4.26 - Generated on Tue Jan 26 09:25:07 2010 - tmdlHdmiTx component API
PHILIPS